The present application relates generally to semiconductor devices, and more particularly to fin field effect transistors (FinFETs) and their methods of fabrication.
Fully-depleted devices such as fin field effect transistors (FinFETs) are candidates to enable scaling of next generation gate lengths to 14 nm and below. Fin field effect transistors (FinFETs) present a three-dimensional architecture where the transistor channel is raised above the surface of a semiconductor substrate, rather than locating the channel at or just below the surface. With a raised channel, the gate can be wrapped around the sides of the channel, which provides improved electrostatic control of the device.
The manufacture of FinFETs typically leverages a self-aligned process to produce extremely thin fins, e.g., 20 nm wide or less, on the surface of a substrate using selective-etching techniques. A gate structure is then deposited to contact multiple surfaces of each fin to form a multi-gate architecture.
FinFETs can be incorporated into a variety of devices, including logic and memory platforms. In devices comprising different functionalities on the same chip, however, it may be desirable to form arrays of fins having distinct fin dimensions and/or intra-fin spacing. One approach for defining plural fins having variable spacing, or pitch, is to cut selected fins from an initial array of fins. However, as will be appreciated, the achievable fin-to-fin spacing with such an approach is limited.
Defining a variable and controllable fin width and pitch between fins in situ has been problematic due to an inadequate lithography processing window resulting in, for example, line-width variability and/or line roughness.